2026年第三届集成电路设计暑期学校-人工智能驱动的先进集成电路设计方法与工具

1.IC设计流程总论

Phases of IC design；IC design process；IC design flow concept；Types of design；IC design types；Comparison of design methods；Classes of problems solved during design；Design level；Problems solved in one level of design

2.规格与设计对象建模

Specification；Digital IC specification；Necessity of technical object design；TO model；TO modeling/simulation；Necessity for TO simulation；Qualitative leaps in modeling

3.仿真与验证方法

Verification methods；Formal verification；Static timing analysis，STA；IC simulation；Purpose of simulation；Gate level simulation；Circuit level simulation

4.全定制IC设计流

Custom design flow；Schematic design goal；Circuit selection；Schematic design；Parametric optimization；Layout design；Transistor layout

5.版图验证与后仿

Layout design rules；Design rule check，DRC；Layout versus schematic，LVS；Layout parasitic extraction，LPE；Simulation of extracted netlist；Deliverables

6.基于STDCell的数字IC设计流

Cell based automated design；Digital IC design flow；Necessary data for digital design flow；Design environment of logic synthesis；Design environment of physical synthesis

7.逻辑综合与前端实现

Basic steps of synthesis；Logic synthesis；Main optimization trade-offs；Basic logic gates；Cell logic model；Cell library logic model file

8.物理综合与后端实现

Physical synthesis；Physical synthesis steps；Floorplanning；Placement；Unit tile；Routing；Circuit optimization during physical synthesis；Clock tree synthesis

9.低功耗与PPA优化

Low power design techniques overview；Main optimization trade-offs；Parametric optimization；Circuit optimization during physical synthesis

10.DFT与芯片测试

Test creation；IC Testing Process and Equipment；Faults and Fault Modeling；Testability Measures；Test Pattern Generation Algorithms for Combinational Circuits；IC Quiescent Current，IDDQ Testing；Design for Testability；Built-in Self Testing，BIST；Scan Testing；Boundary Scan Testing

11.标准单元库基础

Digital standard cell library；Standard cell general information；Standard cell specification example；Standard cell list example；Basic logic gates；Standard cell physical structure；Operating conditions；DC parameters and measurement conditions of digital cells

12.标准单元库设计与表征

Digital standard cell library design flow；Characterization；Characterization flow；Cell logic model；Cell library logic model file；Frame / abstract view of cell；Library exchange format，LEF

13.标准单元库交付物

Digital standard cell library deliverables；Deliverables；Necessary data for digital design flow

1.PDK方法学与设计流程

Lectures: Principles and Design Methodologies of PDK for Advanced Technology Nodes；General Principles and Design Methodologies of PDK；PDK: Definition, Content and Data Flow；Goal of PDK development；Methodology of getting PDK components；The Idea of Interoperability；Interoperable PDK，iPDK: Goal and Benefits；PDK vs. iPDK

2.PDK结构与交付内容

PDK Library；PDK Content: “device_libs”, “documentation”, “icv”, “references”, “SAED_05_PDK”, “scripts”, “starrc”, “sym_libs”, “techfiles” folders；Other files in the PDK package

3.全定制模拟IC设计流程支撑

Full Custom Analog Design Flow: Using Tool Chain；Examples of Schematic Symbol, Spice Model, Technology File, PyCell；Example Script

4. 器件模型与SPICE模型库

Spice Models: Simple model, Model Parameters, Corners, Corner Generation, Spice Model Library；FinFET models: Thin Oxide 0.75V, Medium Oxide 1.2V and Thick Oxide 1.5V FinFET models；Diode models: Standard, 1p2 and 1p5 diode models；Resistor models: Silicided and Unsilicided resistor models；Bipolar Junction Transistor models: PNP and NPN BJTs

5. 5nm器件结构与器件描述

Principles and Design Methodologies of PDK for 5nm Technology Node；Device description: N-channel and P-channel thin oxide FinFET transistors；N-channel and P-channel medium and thick oxide FinFET transistors；NP and PN diodes；Silicided and unsilicided poly resistors；Bipolar Junction Transistors

6.工艺技术文件与物理层定义

Technology Files: Structure, Layer Definitions, Layer Rules, Via Definitions and Constraint Group；Physical layers and parameters: Layer map；Double patterning support, cuts and Design Rules；Routing directions；Physical parameters；Metal stack；Display Resource File: Styles, Packet；Mapping File；Interconnect Technology File

7.参数化单元与版图自动生成

PyCell；PyCells: Integration Mechanism, Implementation, Example, Delivery, Compilation

8.DRC物理规则检查流程

DRC Design Flow；Example of DRC Runset File；DRC Runset File: Structure, Options, Definition Layers, Design Rules

9.LVS版图原理图一致性检查流程

LVS Design Flow；Example of LVS Runset File；LVS Runset File: Structure, Options, Layer Definitions, Connectivity Definition, Device Extraction, Comparison, Property checks

10.寄生参数提取与后仿真支撑

Parasitic Extraction Design Flow；Example of Parasitic Extraction Runset File；Parasitic Extraction Files；Interconnect Technology File

11脚本、参考设计与工具链集成

scripts；references；icv；starrc；Example Script；PDK Library

12.PDK验证、发布与跨工具兼容

The Idea of Interoperability；Interoperable PDK，iPDK: Goal and Benefits；PDK vs. iPDK；PyCell Delivery；PDK Library；documentation

1.逻辑综合总体方法学

Lectures: Logic Synthesis and Optimization based on Fusion Compiler；Synthesis and Optimization；Design levels；Main concepts；Design flow；Main Design Steps；Basic steps of synthesis；Logic synthesis；Logic synthesis steps

2.设计规格与描述

Specification；Design description；Logic circuit；Combinational designs

3.工艺库与单元模型

Cell logic model；Cell library；Library specification and documentation；Example of a technology library；Characterization；Characterization corners

4.工作条件与PVT

Operating conditions；Process and operating conditions；The multiple analysis corners；Types of analysis and optimization；Characterization corners

5.约束与约束驱动综合

Design constraints；Constraint-driven synthesis；Area constraints；Timing closure and constraints；Constraining timing: Setup/Hold；Constraining timing: example

6.时钟环境建模

Clocked environment；Modeling clock latency；Clock modeling summary

7.路径类型与时序建模

Path types；Timing analysis；Static analysis；Path delay；Delay dependencies；Path delay calculation；Factors affecting timing

8.负载/输入转换建模

Effect of output capacitive load；Modeling output capacitive load；Effect of input transition time；Modeling input transition；Load budgeting

9.线负载模型

Wire load model；Wire load: Parasitic effects；Estimating parasitics；The deep-submicron interconnect problem；Problems with Wire Load models；Cost of poor correlation

10.综合优化权衡

Parameter trade-off；Area constraints；Timing closure and constraints；Types of analysis and optimization

11.传统逻辑综合流程

DC NXT synthesis；Logic synthesis；Constraint-driven synthesis；Wire Load models

12.Fusion Compiler流程

FC logic synthesis flow，Compile fusion flow；Logic synthesis in topological mode；Physical Aware，Topological Synthesis；WLM vs Topological mode

13.物理感知综合的数据

The required physical data；Cell library；Technology library；Operating conditions；Design constraints

1.物理综合总体流程与工具链

Lectures: Physical Synthesis and Optimization based on Fusion Compiler；Basic steps and data setup；Tool chain of physical synthesis，ICC2 and Fusion Compiler；Compile fusion flow and stages；Compile Fusion attributes and application options；Restricting Network optimization

2.工艺库、物理库与数据准备

Technology file；Physical data；Resolving references；Library specification and documentation；Process and operating conditions；Characterization corners；Example of a technology library

3.寄生参数与互连建模

Modeling parasitic；tech2itf map file creation

4.Floorplanning / Design Planning

Floorplanning；Floorplanning: aspect ratio；Floorplanning: area utilization；Floorplanning: pin locations；Floorplanning: I/O placement；Floorplanning: creation of site rows；Floorplanning: required actions；Floorplanning: FC/ICC2 dialog；Design planning

5.电源网络规划与综合

Objective of power network；Power grid planning；Top-level power network；Power network synthesis，PNS；PNS flow；PNS requirements

6.I/O规划与封装相关布局

Advanced I/O cell placement；Wire bond；Flip-Chip；Wire bond placement；Flip chip placement；I/O cell physical structures；Flip-chip routed example

7.宏单元与布局约束

Macro placement constraints；Defining placement blockages；Macro keepout margin: padding；Global placement blockages；Routing blockage: route guide

8.标准单元布局与布局优化

Global and detailed placement；Comparison between Placement and Compile engines；Coarse placement；Legalize cell placement；Standard cells placement optimization；Cell density；Timing-driven placement；Timing-driven placement: estimating rnet and cnet before placement

9.拥塞分析与拥塞驱动布局

Routing congestion；Congestion map；Congestion in standard cell placement regions；Congestion caused by poor pin accessibility；Sources of congestion and solutions；Placement issues with congestion；Analyzing the congestion map；Congested design；Congestion-driven placement；congestion vs. Timing-driven placement；Global route for congestion maps；Strategies to fix congestion；Congestion correction；Congestion options

10.可布线性与Pin Access优化

Routing resources；Standard cell routability improvement；Standard cell physical design；IP Pin access improvement

11.时钟树综合与优化

Clock delay problems；Clock tree: general concepts；Clock tree synthesis；Clock skew types；Clock skew types: Global；Clock skew types: local；Clock skew types: useful；Starting point；Build；Insertion delay；CTS goals；CTS prerequisites；Multiple clocks；Multiple synchronous clocks；Generated and gated clocks；Effects of clock tree synthesis；Clock tree optimization；Core CTS and optimization；Clock tree final view

12.布线基础与布线优化

Routing fundamentals；Routing goals；Routing input and output；Global routing: region assignment；Detailed route: vias；Detailed routing: noise；Detailed routing: shielding；Detailed routing: objectives；Routing over macros；Routing and optimization summary

13.后端优化闭环与ECO

Search and repair，ECO；FC/ICC2 based signoff ECO flow

14.物理验证与签核流程

FC/ICC2 based signoff PVR flow

1.AI-driven EDA总体方法学

Lectures: AI-driven EDA Technologies；Introduction to Design Space in IC；Multidimensional parameter space and fundamental concepts of design space exploration in logical and physical designs

2.设计空间、优化目标与约束定义

Optimization objectives and constraints；Defining the multi-dimensional optimization goals including Power-Performance-Area triad and design constraints that bound the solution space；Parameter space；Permutation DSE

3.传统优化算法基础

Traditional optimization algorithms；Heuristic and metaheuristic approaches including simulated annealing, genetic algorithms, and analytic placement

4.机器学习与AI优化方法

Modern Machine Learning-Based and AI-Driven Optimization Methods including Bayesian optimization and reinforcement learning for design space exploration

5.多目标优化与Pareto分析

Multi-Objective optimization and Pareto Analysis；Frameworks for navigating trade-offs between conflicting objectives to identify optimal design configurations；Pareto frontier；Convergence behavior

6.数字IC逻辑与物理设计中的AI优化

CTS；Placement；Routing；Multi-corner；Power-aware RL strategies；7-dimensional search

7.DSO.ai工具与架构

Introduction to Design Space Optimization DSO.ai tool；DSO.ai architecture and targeted optimization methods；DSO.ai optimization algorithms

8.DSO.ai强化学习优化机制

RL engine；Policy network；Reward formulation；Agent-environment loop；RL；PPO；Adaptive flow and Sequential decision-making algorithms；Multi-objective reward shaping and Lagrange adaptation

9.DSO.ai指标跟踪与签核闭环

Metric tracking: WNS, TNS, DRC, EM, SI；Closed-loop signoff driven optimization stages

10.DSO.ai与数字后端工具集成

Integration into IC Compiler II/Fusion Compiler and Cold/Warm runs；Benchmark results & silicon data；Demo DSO.ai in practice

11.模拟IC参数优化方法学

Parametric Optimization of Analog Integrated Circuits: Essence, Necessity, Process, Challenges and Modern Methods

12.模拟IC启发式参数搜索算法

A method for automating the selection of Analog IC parameters using Swarm Intelligence–Based Heuristic Search Algorithms；A special primary population initialization method to accelerate convergence of heuristic search algorithms；Method for initializing the primary population of heuristic algorithms

13.模拟IC仿真加速与搜索效率提升

A method for replacing IC simulation software with artificial neural networks during parametric optimization；A method for improving search efficiency of automated IC parameter selection using heuristic algorithms；A method for reducing the number of simulation calls during parametric optimization

14.ASO.ai模拟IC优化工具实践

Introduction to Parametric Optimization tool of Analog Integrated Circuits ASO.ai；Using ASO.ai in practice to tune analog designs efficiently；The end-to-end flow: setup → specification definition → parametrization → optimization review；Running the optimizer and interpreting results；Define specifications and design parameters for tuning；Demo ASO.ai in practice

1.门级逻辑仿真总体概念

Lectures: Logic Circuit Simulation Technologies；Gate level simulation nature；Gate level simulation goals；Classification of gate level simulation

2.门级仿真输入、输出与测试计划

Inputs and outputs of gate level simulator；testplan；definition；description；logic values

3.逻辑值体系与未知态处理

3 and 5-valued logic rules；Obtaining pessimistic result through U；Obtaining incorrectness through U and Ū；Other troubles of U

4.逻辑模型与模型实现

Logic models；Logic model implementation

5.延迟模型与时序行为建模

Delay models；Impact of delay model；Delay models for gate；Delay model for functional element；Delay model for interconnects；Gate delay model simple example；Accurate gate delay model example

6.冒险现象检测与分析

Static hazard definition；Static hazard detection: algorithm, example；Dynamic hazard definition；Dynamic hazard detection example

7.编译型门级仿真方法

Compiled simulation；Compiled zero delay simulation；Compiled unit-delay simulation；A compiled simulation example；Extension of asynchronous circuit；Compiled model for re-convergent structure；Compiled model for RS flip-flop；Compiled model of branching structure

8.事件驱动门级仿真方法

Event driven gate level simulation；Initialization；Event scheduling；Event optimization；Event queue implementation；Priority event queue；Bucket event queue - time wheel；Event driven simulation process

9.仿真方法比较

Comparison of compiled and event driven simulations

10.故障仿真与故障模型

Fault simulation；Good and fault design examples；Fault models；Parallel fault simulation；Concurrent fault simulation；Parallel pattern single-fault simulation

11.门级仿真语言与实现方式

Gate level simulation languages；Verilog example；C example；HDL vs. Programming language

12.门级仿真控制与执行管理

Gate level simulation control